1. Technical Field
The present invention is related generally to computer systems, and more specifically to computer systems containing cache memories.
2. Background Art
Computer systems generally have several different storage layers defining a memory hierarchy. These layers typically include registers in a central processing unit, main system memory, and mass storage, such as disks. The performance of these different levels is quite different. The processor registers are much faster than system memory, which in turn is significantly faster than access to mass storage.
In order to improve system performance, a cache consisting of a small, fast memory, is often used between the central processor and system memory. The cache takes advantage of the locality of reference phenomenon within computer programs to store data which is likely to be reused into the fast memory.
The use of a cache memory between the central processor and system memory allows the system memory to be designed for high speed access. Transfer of data between the cache memory and the system memory is performed as block transfers which have a length dependent upon the cache memory design. The system memory design can be optimized for block data transfers to take advantage of this. For example, interleaved memory accessing can be used for the main system memory.
In many systems, input/output devices also have access to the main system memory. In systems of this type, the main memory cannot be designed to only support block transfers, because the input/output devices are generally not capable of block data transfers. In fact, many input/output devices, such as keyboards and input/output ports, are single character oriented devices.
Many cache designs for use between the central processor and system memory do not allow use by the input/output devices and overall system performance is adversely affected. Input/output devices must access system memory at their lower performance levels. Although the central processor can operate on data in its cache at any time, a cache miss causes the central processor to wait whenever an input/output device is performing a read to, or write from, system memory.
It would be desirable to provide a computer system which allows efficient access of a system memory by input/output devices. It would also be desirable for a computer system to provide that the performance central processor access to system memory is not greatly degraded during system memory access by input/output devices.